Logic Circuits
Mostrando 1-12 de 53 artigos, teses e dissertações.
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1. Geração de b-splines via FPGA / B-spline generation via FPGA
The b-splines are used in CAD/CAM/CAE systems to represent and define complex curves and surfaces, being adopted by the main computer graphics standards due to features like compact mathematic representation, flexibility and affine transformations. In 3D acquisition systems and integrated CAM-CNC systems, the use of the b-spline in the geometric information
IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia. Publicado em: 10/08/2012
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2. Detecção de defeitos do tipo Resistive-Open em SRAM com o uso de lógica comparadora de vizinhança
The world we live today is very dependent of the technology advance and the Systemson- Chip (SoC) are one of the most important actors of this advance. As a consequence, the Moore s law has been outperformed due to this strong demand on the SoCs for growth, so that new silicon technologies has emerged along with new fault models that decreased the reliabilit
IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia. Publicado em: 30/03/2012
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3. Monitoração dinâmica de asserções para depuração em silício
The increasing demand for shorter time-to-market, combined with increased complexity and performance requirements put a tremendous pressure on post-silicon debug, which is usually the last step prior to chip release. In contrast to pre-silicon techniques, postsilicon debug have two main limitations, controllability and observability, which cause the failure
IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia. Publicado em: 08/08/2011
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4. A novel voltage-mode CMOS quaternary logic design
This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-
Publicado em: 2011
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5. Probabilistic approach for yield analysis of dynamic logic circuits
In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for
Publicado em: 2011
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6. Data processing section for microprocessor-like integrated circuits
A methodology for the design of complex logic VLSI circuits is presented. The target application is deseribed by an algorithm from which the structures of the control section and the data processing section of the integrated circuit are inferred. The Srchltectural aspects are discussed and a model is proposed. A set of functional cells is then presented whic
Publicado em: 2011
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7. Single event transients in logic circuits - load and propagation induced pulse broadening
The generation and propagation of single event transients (SET) in logic gate chains is studied and modeled. Regarding SET generation, we investigate the dependence of the generated SET pulse width on the struck node capacitance. Rising node capacitance may lead to amplified pulse width, indicating that increasing load capacitance alone is not an option for
Publicado em: 2011
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8. Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition / Síntese lógica independente de tecnologia visando múltiplos objetivos, aplicada a funções de múltiplas saídas, empregando composição funcional de AIGs
O emprego de ferramentas de automação de projetos de circuitos integrados permitiu que projetos complexos atingissem time-to-market e custos de produção factíveis. Neste contexto, o processo de síntese lógica é uma etapa fundamental no fluxo de projeto. O passo independente de tecnologia (parte do processo de síntese lógica, que é realizada sem co
Publicado em: 2011
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9. AnÃlise de performance de sÃlitons Ãpticos espaÃo-temporais em guia planar com nÃo-linearidade cÃbico quintica periodicamente modulada e circuitos lÃgicos operando nos regimes Kerr instantÃneo e relaxado. / Performance analysis of the spatio-temporal optical solitons in a planar guide with cubic quintic nonlinearity periodically modulated and logic circuits operating in regimes Kerr instantaneous and relaxed.
In this work, the propagation and stability of spatiotemporal optical solitons (or optical bullets) in a planar waveguide with periodically modulated cubic-quintic nonlinearity is presented numerically as a function of the amplitudes of modulation , the frequency of modulation and the propagation distance .With the objective of ensure the stability and preve
IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia. Publicado em: 03/03/2010
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10. An estimation method for gate delay variability in nanometer CMOS technology
In the nanoscale regime of VLSI technology, circuit performance is increasingly affected by variational effects such as process variations, power supply noise, coupling noise and temperature changes. Manufacturing variations may lead to significant discrepancies between designed and fabricated integrated circuits. Due to the shrinking of design dimensions, t
IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia. Publicado em: 2010
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11. Estudo e implementação de lógica adiabática para circuitos integrados com baixo consumo / Study and implementation of adiabatic logic for low-power integrated circuits
Este trabalho está inserido no ramo de microeletrônica, mais especificamente em circuitos integrados de baixo consumo. Trata-se de um campo importante visando diminuir o consumo de energia mundial, possibilitar a utilização de equipamentos com fonte de baterias por mais tempo e diminuir o custo de resfriamento de circuitos, além do consumo de energia do
Publicado em: 2010
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12. CMOS digital integrated circuit design faced to NBTI and other nanometric effects / Projeto de circuitos integrados digitais CMOS face ao NBTI e outros efeitos nanométricos
Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tec
IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia. Publicado em: 2010