Detecção de defeitos do tipo Resistive-Open em SRAM com o uso de lógica comparadora de vizinhança


IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia




The world we live today is very dependent of the technology advance and the Systemson- Chip (SoC) are one of the most important actors of this advance. As a consequence, the Moore s law has been outperformed due to this strong demand on the SoCs for growth, so that new silicon technologies has emerged along with new fault models that decreased the reliability of these devices. SoCs built using Very Deep Sub-Micron technology have a great number of interconnections, increasing the occurrence of Resistive-Open defects that occur on these interconnections up to the point where Resistive-Open defects have become the most important responsible for defective SoCs escaping the manufacturing tests. According to SIA Roadmap s projection, the area consumed by the SRAM on the SoC will be around 95% of the available area, knowing these memory have a great number of interconnections there is also a great probability of occurring Resistive-Open defects on the SRAM circuits which will compromise the overall SoC reliability. When found on SRAMs cells, these defects are able to cause dynamic and static functional faults according to its size, where static faults are sensitized by performing only one operation at the SRAM cell, while dynamic are sensitized by two or more operations. The most common manufacturing tests used to detect defective SoCs are today unable to detect dynamic faults caused by weak Resistive-Open defects. March test performs access on the memory with the intention of sensitizing the faults and detect them as consequence. Due to the higher number of operations necessary to sensitize dynamics faults, this test is not able to detect them properly. Another test is the Iddq test, which is able to detect the presence of defects by monitoring the overall current consumption of a SoC while it s being excited by a known vector of data on its inputs. The consumed current is compared to thresholds or to another similar device that is being excited on the same way. Iddq test is not able to distinguish the variations on current caused by process variations or defects presence. There is an other type of test using On-Chip Current Sensors (OCCS) with March tests that performs current monitoring on the circuits of the SoC and compare them with a threshold in order to set a ag when the monitored current gets higher or lower than a con gured thresholds. Because the mentioned test uses threshold, it is not able to detect Resistive-Open defects that could happen in any node, with any size, in the SRAM cell performing any operation. In this scenario the current consumption could be higher or lower than the defectless current consumption of a cell, making impossible to detect defects using thresholds. By all that, the objective of this dissertation is to propose a defect detection technique able to overcome the three mentioned limitations of preview explained tests. For that, OCCS are along with March test, but a Neighborhood Comparator Logic (NCL) has been included with the objective to perform the detections itself, removing from the OCCS the mission of nding defects. Now the OCCS is only responsible in converting the monitored current consumption signal to a one bit PWM digital signal. In this form, no threshold will be required because the NCL will obtain the reference of the correct current consumption (behavior reference) within the SRAM circuits, by comparing the neighboring cells and adopting the most common behavior as the reference one, so that it will detect those cells that behave di erently from the reference as defective ones. The neighborhood s cells are excited in a parallel form by the test processor, which performs a March test algorithm. The NCL, the OCCS and the March test, together, compose the proposed Resistive-Open detection technique, which has been validated on this work. As result, the proposed technique has shown being able to detect all of the 10 million defective cells of a 1Gbit SRAM containing the hardest defect to detect (small ones). No defective cell has escaped the simulated test and there was only 294,890 good cells being wasted, which represents 0.029% of the simulated SRAM cells. All of that, by costing only the equivalent to the area of 56 SRAM cells per monitored column and a manufacturing test that performs 5 operations per line of the SRAM.


circuitos eletrÔnicos algoritmos microeletrÔnica engenharia elÉtrica engenharia eletrica tolerÂncia a falhas (informÁtica)

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