Probabilistic approach for yield analysis of dynamic logic circuits

AUTOR(ES)

Brusamarello, Lucas

DATA DE PUBLICAÇÃO

2011

RESUMO

In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-NOR circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100 .

ASSUNTO(S)

design for yield microeletronica monte carlo methods probabilistic analysis process variability vlsi yield estimation

Documentos Relacionados

• Shifter circuits: a computational strategy for dynamic aspects of visual processing.
• An efficient mechanical-probabilistic approach for the collapse modelling of RC structures
• Minding the gap between logic and intuition: an interpretative approach to ethical analysis
• DNA for nano-bio scale computation of chemical formalisms using Higher Order Logic (HOL) and analysis using an interdisciplinary approach
• An empirical analysis of training protocols for probabilistic gene finders