Modelamento, projeto e caracterização de transistores verticais DMOS de potencia e estruturas de alta tensão compativeis com a tecnologia CMOS

AUTOR(ES)
DATA DE PUBLICAÇÃO

1989

RESUMO

The objective of this thesis is to investigate the design viability of power and high-voltage VDMOS transistors, built in a standard CMOS process, usually used for low-voltage applications. Also. the monolithic integration possibility of power VDMOS devices and low voltage logic control circuitry is verified. First of all, follows a discusion on some theoretical aspects of the available technologies, specially the CMOS standard technology, P I N planar "junction breakdown modeling and the conduction resistance ( on - resistance ) modeling for VDMOS transistors. Afterwards, the design of a test chip containing high-voltage diodes and VDMOS transistors is discussed, as well as the electric characterization of the prototypes fabricated in a P-well, 3 micron. single poly and single metal CMOS process. The experimental results show that 100-uolt and 75 mohm . cm2 VDMOS transistors can be designed on the standard CMOS process used. A further optimization loading to an on-resistance reduction is possible if the process could be started with N- I N+ epitaxial silicon wafers, resulting in a device performance similar to the commercial ones available nowadays. The monolithic fabrication of a VDMOS transistor and some low-uoltage control logic was also found to be fauorable. Resume: Ce travail a été developpé dans le but de rechercher une méthode capable de viabilizer le projet d un transistor VDHOS de puissance et haute tension, en s utilisant d un processus CHOS conventionnel, de basse tension; ensuite, par des essais experimentaux, verifier Ia possibilité d integration monolithique du dispositif VDMOS et d un circuit logique de controle a basse tension. Tout d abord, sont presentés les aspects theoriques des technologies disponibles actuellement, speciallement Ia technologie CMOS standard, de Ia tenue en tension de jonctions planar et de Ia résistance a l etat passant des transistors VDMOS. En suite, sur Ia base theorique developée, on discute le projet et Ia characterization électrique d un prototype de test, contenant des diodes et des transistors VDMOS à haute tension, dans le cadre d un processus CMOS caisson P, 3 microns, avec une couche de polysilicium et une couche de metal. Les resultats experimentaux ont montre Ia reélle possibilité de construction des transistors VDMOS de 100 volt et 75 mohm . ca2. La resistance à l etat passant pourrait être optimizée par l utilization des substrats epitaxiaux du type N- / Nt, resultants des performances similaires aux dispositifs commerciaux actuels. La construction monolithique dês circuits logiques de controle a favorable.

ASSUNTO(S)

transistores semicondutores de metal e oxido

ACESSO AO ARTIGO

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