Logical Circuits
Mostrando 1-11 de 11 artigos, teses e dissertações.
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1. Electromechanical Impedance - Based Structural Health Monitoring Instrumentation System Applied to Aircraft Structures and Employing a Multiplexed Sensor Array
ABSTRACT: The electromechanical impedance method has been seen as a promising tool for structural health monitoring regarding different types of structures and purposes. Most importantly, this method can be used in real-time applications. Frequently, massive, high-cost, single-channel impedance analyzers are used to process the time domain data, aiming at ob
J. Aerosp. Technol. Manag.. Publicado em: 2015-09
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2. Otimização de interconexões através de posiocionamento e síntese lógica / Interconnects optimization through placement and logic synthesis
No fluxo atual de projeto de circuitos digitais modernos é difícil estimarmos os atrasos que ocorrem nas interconexões, especialmente antes do posicionamento das células. E quando os atrasos são corretamente avaliados, após o posicionamento, devido às diferentes estruturas de dados utilizadas para as diferentes etapas do projeto, eles não podem ser r
Publicado em: 2010
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3. Learning about brain physiology and complexity from the study of the epilepsies
The brain is a complex system, which produces emergent properties such as those associated with activity-dependent plasticity in processes of learning and memory. Therefore, understanding the integrated structures and functions of the brain is well beyond the scope of either superficial or extremely reductionistic approaches. Although a combination of zoom-i
Brazilian Journal of Medical and Biological Research. Publicado em: 2009-01
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4. Paraconsisted computation : a logic approach to quantum / Computação paraconsistente : uma abordagem logica a computação quantica
This work provides evidences to view computational complexity as logic-relative, by introducing new models of computation through non-classical logics and by studying their features with respect to computational expressivity and efficiency. From this point of view, we suggest a new way to study the efficiency of quantum computational models consisting in the
Publicado em: 2009
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5. Synthesis of circuits with memory in multilevel logic / Síntese de circuitos com memória em lógica multinível
With the advanced in the technology VLSI (very Large Scale Integration) of the integrated circuits, broad interest has been generated regarding circuits that utilize more than two logical levels for the discrete representation of signals. These circuits are named, logic circuits of multiple values (MVL) and offer a great potential for the design of VLSI, bec
Publicado em: 2008
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6. Combinational digital circuit in multi-valued logic / Circuitos digitais combinacionais na lógica de múltiplos valores
The combinational digital circuits are designed in binary logic known as Switching Algebra, and depending of the complexity have limitations, some of them are consumption of energy and the size of the circuits generated by the number of interconnections, one alternative to solve this problem is the use of Multilevel Logic also known as Multi-valued Logic (MV
Publicado em: 2008
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7. Da computação paraconsistente a computação quantica
As diferentes interpretações da mecânica quântica levanta sérios problemas filosóficos a respeito da natureza do mundo físico e do estatuto das teorias físicas. Tais interpretações desempenham um papel importante na compreensão dos modelos de computação quântica, e por sua vez os modelos de computação quântica abrem a possibilidade de se con
Publicado em: 2006
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8. Proposta de um registrador ciclico para logica multi-valores e aplicação em um multiplicador quaternario / The cyclical register for MVL circuits (Multi-valued logic) and quaternary multiplier
The Cyclical Register for MVL circuits (Multi-valued Logic) proposed is composed by NMOS and PMOS Transistors. This circuit uses the advantage of certain secondary characteristics (normally undesirable) of the MOS transistors. One peculiarity of this register is that the logical levels are defined by itself with a very high precision ; this, permits to incre
Publicado em: 2005
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9. NEW METHODOLOGY TO THE ESTIMATIVE OF CAPACITANCE AND POWER CONSUMPTION OF COMPLEX LOGIC GATES CMOS AT LOGIC LEVEL / NOVA METODOLOGIA PARA A ESTIMATIVA DE CAPACITÂNCIA E CONSUMO DE POTÊNCIA DE PORTAS LÓGICAS COMPLEXAS CMOS NO NÍVEL LÓGICO
This dissertation presents a methodology of capacitance estimation and power consumption in CMOS circuits combinational constituted basically of complex logic gates at logic level. The main objective in the development of this method is to provide a fast estimate of the power consumption of circuits at the logical design gates. Of this form, the considered m
Publicado em: 2005
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10. A GRAPH PARTITIONING HEURISTIC FOR THE PARALLEL PSEUDO-EXHAUSTIVE LOGICAL TEST OF VLSI COMBINATIONAL CIRCUITS / UMA HEURÍSTICA DE PARTICIONAMENTO DE GRAFOS PARA O TESTE LÓGICO PSEUDO-EXAUSTIVO EM PARALELO DE CIRCUITOS COMBINACIONAIS VLSI
O teste lógico de circuitos integrados VLSI é parte indispensável de sua fabricação e projeto. O enfoque pseudo-exaustivo para o teste lógico de circuitos integrados consiste em particionar o circuito original a ser testado em subcircuitos com um reduzido número de entradas, que são então testados em paralelo de forma exaustiva. Neste trabalho apres
Publicado em: 1994
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11. Contribuição a minimização e simulação de circuitos logicos
This work deals with some aspects related to synthesis, analysis and simplification of logic circuits. The boolean algebra is introduced through basic axioms, as well as the dalgorithm for fault detection studying logical circuits. For the minimization of boolean functions a procedure that yields a quasi-minimum cover to the functions is presented. It is bas
Publicado em: 1989