Proposta de um registrador ciclico para logica multi-valores e aplicação em um multiplicador quaternario / The cyclical register for MVL circuits (Multi-valued logic) and quaternary multiplier

AUTOR(ES)
DATA DE PUBLICAÇÃO

2005

RESUMO

The Cyclical Register for MVL circuits (Multi-valued Logic) proposed is composed by NMOS and PMOS Transistors. This circuit uses the advantage of certain secondary characteristics (normally undesirable) of the MOS transistors. One peculiarity of this register is that the logical levels are defined by itself with a very high precision ; this, permits to increase the logic to many values. Since it is not limited to ternary or quaternary logic (more used MVLs), its use can be extended to decimal, hexadecimal and others. The proposed cyclical register, besides storing the multi-value data with precise voltage level, still, supplies the output with any possible logical shift without the degradation of precision. This register will allow the development of logical circuits as counter, toggle switch, shift register, flip-flop in several levels, shift of value, D/A and A/D converter, etc? Some advantages that this circuit offers is its high frequency response and its minor dependency of the parameter of the transistors, providing a robustness comparable to the current binary circuits. As an application of this proposed Register a Quaternary Multiplier is presented and compared with the Binary Multiplier with the same technology. On this paper the circuits will be developed and simulated in the OrCad (Pspice [01]), using the transistors models NMOS and PMOS supplied by foundry AMS (Austria Micro Systems) detailed in the Appendix I. The Cyclical Register for MVL circuits was presented by the author in the Congress SUCESU 2005 in March 31st, 2005 in Belo Horizonte, MG, Brazil

ASSUNTO(S)

cyclical register logica a multiplos valores eletronica digital mvl logic multi-valued logic

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