Implementation of an Ethernet 10/100Mbps core with Avalon interface for Nios II processor from Altera / Implementação de um módulo Ethernet 10/100Mbps com interface Avalon para o processador Nios II da Altera

AUTOR(ES)

Ricardo Menotti

DATA DE PUBLICAÇÃO

2005

RESUMO

This work presents the implementation of a network Ethernet 10/100Mbps core with interfaces to Avalon bus for using with the Nios II processor from Altera. The Ethernet technology was implemented in reconfigurable computing and was based in the OpenCores MAC 10/100 available on Internet. The project was developed for embedded systems applications, more specifically for a mobile robot in development at Reconfigurable Computing Laboratory from ICMC/USP. The core was incorporated to SoPC Builder tool’s library from Altera, aiming to facilitate the integration with others projects. To development and system tests were used Quartus II and ModelSim, and two Nios Development kit Statix Edition for project validation. The boards were linked peer-to-peer, without use analog transceivers.

ASSUNTO(S)

computação reconfigurável soc ethernet sopc embedded systems ethernet sopc sistemas embutidos fpga soc fpga reconfigurable computing

Documentos Relacionados

• A power estimation design for the Altera Nios II processor
• Técnicas de profiling para o co-projeto de hardware e software baseado em computação reconfigurável aplicadas ao processador softcore Nios II da Altera
• Design and implementation of a PDC-ComPacket decompressor in a SPARC processor
• UM PROCESSADOR GRÁFICO PARA O SISTEMA CYGNUS
• COMMUNICATION PROCESSOR FOR CYGNUS COMPUTER