Determinação de regras de projeto e de parametros de simulação de um processo nMOS para fabricação de circuitos integrados

AUTOR(ES)
DATA DE PUBLICAÇÃO

2002

RESUMO

This work presents the development and the improvement of an nMOS device fabrication process used for microelectronics research and education. The electric characterization and the parameter extraction procedure for SPICE simulation were also presented. Initially, a study of the nMOS device fabrication process used in courses and researches at the center for semiconductor components (CCS/UNICAMP) was accomplished. Following, another fabrication process with some new parameters was proposed. The fabrication process structure is described from the basic stages of fabrication, which were researched, simulated, implemented and characterized. Some of the electrical and technological criteria are related and tested, seeking to propose improvements in the CCS fabrication process. The nMOS device fabrication processes steps and electrical characteristic simulations were obtained by semiconductor devices software simulator. The adjustments in the simulation parameters, were obtained after comparisons with the experimental device. The final process sequence was applied in the fabrication of tests wafers and in the wafers already used in CCS courses. Enhancement and depletion transistors with 5µm effective channel length, capacitors, logic gates and tests structures were fabricated. By using a new proposed process, transistors with 1.7µm minimum effective channel length and junction depth of 0.2µm were fabricated. After the wafer fabrication, the SPICE simulation parameters were extracted following the traditional methodology. Looking for models descriptions that keep up with technology progress and with devices dimensions reduction, the BSIM3v3 simulation model was presented. For parameters extraction and model validation, wafers provided from IMEC-Belgium were used. The results showed that the simulators models when well performed, even in the extraction methodology or in the mathematical equations, may represent the device behavior with good precision. In conformity with the publications regarding this subject, the agreement between the fabricated devices and the simulated devices curves is satisfactory, with a imprecision smaller than 10%, either in small or long geometry devices dimensions. Using this results, a design kit for devices and circuits projects had been made available at CCS.

ASSUNTO(S)

silicio transistores de efeito de campo spice (programa de computador)

ACESSO AO ARTIGO

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