Uma arquitetura para verificação de blocos de computação gráfica em hardware

AUTOR(ES)
DATA DE PUBLICAÇÃO

2005

RESUMO

This work presents, analyzes and validates a novel verication architecture for computer graphics cores. This architecture has four stages and it is supported by two techniques: the automatic verication and the high and low level verication. The rst stage denes and implements a high level executable especication for the computer graphics core. The second stage implements the Register Transfer Level (RTL) implementation and assertions are written. The last two stages are responsible for the sub-block verication and the system level verication of the design. In order to improve the verication stage performance, this work presents a graphical tool (GV T) and a Computer Aided Design tool (V 2T) that provides automatic verication at a higher and lower level of abstraction. Finally, a case study is perfomed to validate the proposed architecture of verication. This case study includes the design, verication and prototyping of a computer graphics core for an automatic optical inpection platform.

ASSUNTO(S)

arquitetura de computadores teses computação teses.

ACESSO AO ARTIGO

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