Synthesis of circuits with memory in multilevel logic / Síntese de circuitos com memória em lógica multinível

AUTOR(ES)

Meliton Apaza Tito

DATA DE PUBLICAÇÃO

2008

RESUMO

With the advanced in the technology VLSI (very Large Scale Integration) of the integrated circuits, broad interest has been generated regarding circuits that utilize more than two logical levels for the discrete representation of signals. These circuits are named, logic circuits of multiple values (MVL) and offer a great potential for the design of VLSI, because their capability to store and transmit more information per digit, i.e. the higher the radix the lower the number of needed digits to represent a value. As with the binary circuits, the MVL circuits are based on an MVL Algebra and are comprised of the combinational and the sequential circuits. This work proposes a method for the synthesis of MVL sequential circuits (with memory) that involve: 1) a description of the generated Algebra MVL; 2) the synthesis of memory elements (latch RS, RS flip-Flop-flip D Flip-flop flop Slave Master); 3) definition of the MVL Clock; 4) the simplification methods to MVL sequential circuits; and 5) methodology for the synthesis for MVL sequential circuits presented in this work. Simulations demonstrate soundness of the proposed methodology.

ASSUNTO(S)

synthesis of sequential circuits mvl multivalued lógic síntese de circuitos seqüenciais mvl engenharia eletrica mvl memories redução de estados minimization of states memorias mvl lógica de múltiplos valores

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