Projeto e implementação em VLSI de uma rede neural auto-organizavel usando sintese automatica de auto nivel

AUTOR(ES)
DATA DE PUBLICAÇÃO

1997

RESUMO

: A Kohonen-based (SOFM - Self-Organizing Feature Map ) artificial neural network was simulated, modelated and hardware implemented in a VLSI circuit. A Top-Down methodological approach was used by using ANSI-C and VHDL (Very High Speed Circuits, Hardware Description Language). The original SOFM algorithm was lightly modified for customizing to the hardware implementation requirements. After a high-level modeling and simulation, a fully-digital VLSI Neuroprocessor chip prototype was designed and manufactured in a CMOS 1.2microns technology. Most of the circuits structures of Neuron were automatically generated from a VHDL RTL description using automatic synthesis, the others were obtained trough conventional schematics procedure. After functional verification, the resulting circuits were optimizated (drived by silicon area minimization) and mappe d to the AMS technology, a 2-level metal process from Austria Mikro Systeme. The Neuron cell has 6 bi-directional 3-bits capability connections, used for neighbours communication, Allowing to implement a hexagonal type dynamic Nc(t) neighbourhood. Both Nc(t) radio and gain Alfa function may be programmed by using a set of registers, allowing high flexibility for studying different SOFM algorithm convergence conditions. A second chip was designed and manufacture dusing a AMS CMOS0.8 microns technology for implementing a competitive on-chip learning. This circuit is part of a WTA (Winner-Takes-All) block used for determine a winner cell in each epoch of the self-organized training phase. Some differences were observed after comparing measures and simulation results

ASSUNTO(S)

algoritmos paralelos arquitetura de computador computadores - circuitos circuitos integrados digitais redes neurais (computação)

ACESSO AO ARTIGO

Documentos Relacionados