IVM: uma metodologia de verificaÃÃo funcional interoperÃvel, iterativa e incremental

AUTOR(ES)

Bruno OtÃvio Piedade Prado

DATA DE PUBLICAÇÃO

2009

RESUMO

The growing demand for electronic devices and its even higher integration capability created extremely complex systems in chips, known as System-on-Chip or SoC. In a opposite way to this tendency, the time-to-market for these systems be built have been continually reduced, forcing much more functionalities be implemented in even shorten time periods. The final product quality control is assured by the Functional Verification activity that consists in a set of techniques to stimulate a system in order to find bugs. This activity is extremely expensive and necessary, responding to around 80% of final product cost. In this context this work is inserted on, proposing a Functional Verification methodology called IVM that will provide all conditions to deliver high quality systems, while keeping the hard time restrictions imposed by the market. Based in well known and trusted methodologies, as OVM and VeriSC, the IVM defined an architectural organization and an activity flow that incorporates features of both approaches that were separated from each other. This techniques and concepts integration resulted in a more efficient verification flow, allowing systems to meet the desired budget, schedule and quality

ASSUNTO(S)

verificaÃÃo funcional verisc functional verification ovm digital systems ovm soc ciencia da computacao functional coverage soc sistemas digitais cobertura funcional verisc

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