Aquarius II â Uma plataforma para desenvolvimento de sistemas dinamicamente reconfigurÃveis baseada no sistema operacional uCLinux

AUTOR(ES)
DATA DE PUBLICAÇÃO

2007

RESUMO

The programmable logic devices, FPGAs (Field Programmable Gate Arrays) have been used for a long time as tools for digital circuits prototyping. However, this reality has changed since the computational power of these devices increased and cost decreased. Besides, the FPGAs in use nowadays consume less energy than a conventional CPU to do the same work. Another characteristic, which brings a lot of possibilities, is the capacity of run-time reconfiguration (dynamic reconfiguration). All of this advances allow the use of FPGAs not only in typical applications, as embedded systems, but also in high performance systems, which process massive data. However, despite all advantages presented, this technology has not been largely used on computational applications. There are a lot of reasons for this, among them the requirement of minimal digital electronic knowledge to make the IPCores development possible; the complexity of the these systems development process; the high costs with tools licenses and development boards and the low portability of the developed applications. The goal of this work is to provide a reconfigurable platform able to efficiently manage the resources provided by FPGAs, through an operational system. The proposed platform was named Aquarius II and was based on the Aquarius Platform developed at CIn-UFPE. The platform has hybrid architecture and consists of a Stratix II FPGA from Altera, responsible for the reconfiguration control and data traffic, and on a Virtex-II FPGA from Xilinx which is in fact, the reconfigurable element. We added to this platform: a communication module (IPCommCore) that is responsible for the data traffic from the operational system to the reconfigurable device memory; a device driver for the uCLinux operational system which controls the communication through the communication module IPCommCore; and a default communication interface, for the reconfigurable cores that are to be developed, was also defined. To validate this interface a multiplier core was developed for the Virtex-II and was used as a case study. This platform will allow researches in fields that seek for this technologyâs benefits, like embedded and high performance systems. The development of computational systems that use reconfigurable hardware in their architecture is still complex and not common. Nevertheless, proposals like the one presented in this work aim at solving or attenuating the cited problems and sensitively changing this reality making solutions that use this technology viable and more popular

ASSUNTO(S)

uclinux fpgas dynamic reconfiguration uclinux ip-cores reconfiguraÃÃo dinÃmica ip-cores kfpgas device drivers ciencia da computacao device drivers

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