A Methodology to explore the design space of memory hierarchies for embedded systems / Uma Metodologia para ExploraÃÃo do EspaÃo de Projeto de Hierarquias de MemÃria para Sistemas Embarcados

AUTOR(ES)

Pablo Viana da Silva

DATA DE PUBLICAÇÃO

2006

RESUMO

In platform tuning, memory hierarchy is an important element to be optimized. Many cache configurations need to be evaluated in order to find out the best choice in terms of performance, silicon area, or power consumption to an application. Most models to estimate those metrics depend on the cache size parameters and their respective miss rate. Instead of using traditional simulation tools to estimate cache miss rate through several cache simulations, we propose a simplified yet efficient technique to estimate the miss rate of many different cache configurations in just one single-pass simulation. The approach basically proposes the generation of locality and conflict tables, which reflects the addressing behavior properties of the application. The proposed technique intends to make the miss estimation easier and the cache exploration faster. Since the table structure is plainly based on elementary bitwise operations of comparison and shifting, flexible software-based approaches can be considered to implement the proposed technique. Additionally, in order to support cache tunning for multiple applications, the cache configuration subsetting problem is exhaustively presented and an efficient solution is discussed. Adapted from a technique for segmenting time series, the results heuristically obtained for selecting optimal cache configurations offer quality comparable to the exhaustive one. Such contribution allows the tuning of a configurable cache to a set of applications with a smallest number of optimal cache configurations, taking into consideration the energy consumption

ASSUNTO(S)

embedded systems hierarquia de memÃria configurable cache optimization simulaÃÃo single-pass ajuste de plataformas ciencia da computacao memory hierarchy platform tuning otimizaÃÃo de cache configurÃvel single-pass simulation sistemas embarcados

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