Uma metodologia para depuraÃÃo de hardware, usando a ferramenta de CAD chipscope pro

AUTOR(ES)
DATA DE PUBLICAÇÃO

2006

RESUMO

The present work proposes a low cost approach for digital systems projects debug in FPGAs. This approach offers an ambient for projects debug based in FPGAs. The approach uses the pattern JTAG to do the readback of the simulation result signs of the user s project. The Signs visualization is made through the ambient ChipScope Pro of XilinxÂ. However is not possible to inject test vectors or to define break points with ChipScope Pro. Being like this a hardware component (injector vectors module) it was developed to control the vectors injection in the user s project. A graphic interface was also created, allowing the definition and send of the vectors through the parallel port of a PC host. The test vectors are defined in high level through a file text, containing simulation parameters. The resident file in the computer host is sent to FPGA, through parallel port. Two modules were used as case study for validation of the approach. The first makes use of a memory control access protocol for devices of I/O. Already the second uses an USART, which was developed by the team of the project Brazil-Ip/FÃnix. Good results were reached and they are presented in this dissertation

ASSUNTO(S)

ciencia da computacao computer architecture arquitetura de computadores fpga fpga reconfiguration reconfiguraÃÃo

ACESSO AO ARTIGO

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