Particionamento Temporal Acoplado a Escolha de Componentes para AplicaÃÃes de ComputaÃÃo ReconfigurÃvel

AUTOR(ES)
DATA DE PUBLICAÇÃO

2008

RESUMO

􀀫􀀖􀀁 􀀉􀀎􀀃􀀁 􀀍􀀋􀀈􀀉􀀁 􀀼􀀃􀀋􀀊􀀈􀀕􀀁 􀀉􀀎􀀃􀀊􀀃􀀁 􀀽􀀋􀀈􀀁 􀀋􀀖􀀁 􀀅􀀖􀀆􀀊􀀃􀀋􀀈􀀃􀀁 􀀇􀀗􀀁 􀀅􀀖􀀉􀀃􀀊􀀃􀀈􀀉􀀁 􀀌􀀼􀀁 􀀉􀀎􀀃􀀁 􀀐􀀊􀀇􀀚􀀊􀀋􀀓􀀓􀀋􀀌􀀍􀀃􀀁 􀀍􀀇􀀚􀀅􀀆􀀁 􀀄􀀃􀀔􀀅􀀆􀀃􀀈􀀁 􀀍􀀅􀀾􀀃􀀁 􀀔􀀆􀀕􀀖􀀗􀀅 􀀋􀀖􀀄􀀅 􀀏􀀆􀀘􀀙􀀗􀀚􀀁 􀀗􀀇􀀊􀀁 􀀋􀀆􀀆􀀃􀀍􀀃􀀊􀀋􀀉􀀅􀀇􀀖􀀁 􀀇􀀗􀀁 􀀋􀀐􀀐􀀍􀀅􀀆􀀋􀀉􀀅􀀇􀀖􀀈􀀁 􀀉􀀎􀀋􀀉􀀁 􀀎􀀋􀀔􀀃􀀁 􀀍􀀅􀀓􀀅􀀉􀀃􀀄􀀁 􀀐􀀃􀀊􀀗􀀇􀀊􀀓􀀋􀀖􀀆􀀃􀀁 􀀗􀀇􀀊􀀁 􀀈􀀇􀀗􀀉􀀽􀀋􀀊􀀃􀀁 􀀅􀀓􀀐􀀍􀀃􀀓􀀃􀀖􀀉􀀋􀀉􀀅􀀇􀀖􀀕􀀁 􀀌􀀃􀀆􀀋􀀒􀀈􀀃􀀁 􀀇􀀗􀀁 􀀆􀀇􀀓􀀐􀀍􀀃􀀤􀀅􀀉􀀼􀀁 􀀇􀀊􀀁 􀀍􀀋􀀊􀀚􀀃􀀁 􀀋􀀓􀀇􀀒􀀖􀀉􀀁 􀀇􀀗􀀁 􀀐􀀊􀀇􀀆􀀃􀀈􀀈􀀃􀀄􀀁 􀀄􀀋􀀉􀀋􀀢􀀁 􀀝􀀊􀀃􀀋􀀈􀀁 􀀋􀀈􀀁 􀀙􀀂􀀃􀀂􀀒􀀌􀀛􀀅 􀀜􀀂􀀃􀀍􀀌􀀛􀀅 􀀆􀀈􀀊􀀎􀀇􀀗􀀗􀀕􀀁 􀀝􀀇􀀛􀀇􀀎􀀊􀀋􀀋􀀑􀀍􀀂􀀎􀀌􀀒􀀂􀀊􀀍􀀗􀀕􀀁 􀀓􀀋􀀌􀀃􀀇􀀗􀀅 􀀆􀀈􀀊􀀎􀀇􀀗􀀗􀀕􀀁 In the last years, there was an increase of interest by the programmable logic devices like FPGAs and CPLDs, for acceleration of applications that have limited performance for software implementation, because of complexity or large amount of processed data. Areas as Digital Signal Process, Telecommunications, Images Process, Bioinformatics and High Performance Scientific Computation take advantages of this tecnology. This interest can be justified by several reasons, such as: The large improvement in microelectronics process have allowed the design of high density FPGAs with capacity for implementation of high complexity systems with millions of logic equivalent gates. This technology improvement also implies in devices working at frequency of hundreds of megaherts, allowing the implementation of systems with very high performance approach. In the last years, the speed of moderns processors is stable in order of 3GHz. This speed stagnation is firstly because of the limitation of heat dissipation capacity, in case of high operation frequency. Therefore, a possible solution for performance demand shoud be based on the exploration of new parallel architectures, like CPUs Multi-Cores and FPGAs. Implementations based on FPGAs execute more computations with reduced energy consumption, in comparison with standard CPUs and Multi-Cores. The energy consumption is a hard problem for increasing of computational power in high performance systems, with impact in the viability, installation cost, operation and system maintenance. Reconfigurable systems based on FPGAs are today a good alternative architecture in terms of performance, in several application domains with an increasing number of cases in commercial applications. In spite of these advantages and high flexibility, with parallelism exploration, the problem for the FPGA popularization is the difficulty for converting high level descriptions, as C and C++, to FPGA hardware descriptions. Especially, the Temporal Partitioning of the Applications is the fundamental step in the generation of high quality implementations. This Thesis contributes to the reduction of the programming difficulty in Reconfigurable Computer Systems (RCS). A Temporary Partitioning Methodology that considers the reuse of IP-Cores, chosen from several available options in a components library, is proposed. The goal is the otimization of the use of the FPGA resources. The proposed methodology explores several possibilities for the tasks mapping in hardware, as several temporary partitions composed by task sub-sets. In the best of our knowledge, two other methods have been proposed in the literature, by Vemuri and Ouni, to try to solve the problem of Temporal Partitioning presentend in this Thesis. However, the experimental results, described in this Thesis, demonstrate the advantages of our methodology. Besides, the presented methodology is the first, in the best of our knowledge, that uses Tabu Search method for Temporary Partitioning in Reconfigurable Systems, with the components choice methodology based on a IP-Core Library for tasks implementation in FPGA

ASSUNTO(S)

ciencia da computacao exploraÃÃo de espaÃo de projeto particionamento temporal design space exploration fpgas temporal partitioning fpgas

ACESSO AO ARTIGO

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