New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
AUTOR(ES)
Abate, F.
DATA DE PUBLICAÇÃO
2011
RESUMO
The growing availability of embedded processors inside FPGAs provides unprecedented flexibility for system designers. The use of such devices for space or mission critical applications, however, is being delayed by the lack of effective low cost techniques to mitigate radiation induced errors. In this paper a non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented. The proposed approach does not require modifications in the processor architecture or in the application software. The experimental validation of this approach through fault injection is described, the corresponding results are discussed, and the addition of a write history table as a means to reduce the performance overhead imposed by previous implementations is proposed and evaluated.
ASSUNTO(S)
embedded processors reliability microeletronica sistemas embarcados single event effects lockstep checkpoint rollback recovery fault injection
ACESSO AO ARTIGO
http://hdl.handle.net/10183/27627Documentos Relacionados
- Designing single event upset mitigation techniques for large SRAM-Based FPGA components
- Projeto de uma Nova Arquitetura de FPGA para aplicações BIST e DSP
- Implementação de uma arquitetura para binarização de imagens em FPGA
- A time Petri net based approach for software synthesis in Hard Real-Time embedded systems with multiple processors
- Proposta de uma arquitetura de processamento de sinais utilizando FPGA