Exploração do espaço de projeto de arquiteturas reconfiguráveis em arranjos / Design space exploration for array reconfigurable architectures

AUTOR(ES)

Marcos Vinicius da Silva

DATA DE PUBLICAÇÃO

2006

RESUMO

Current applications of signal processing in embedded systems demand hardware solutions with high processing power and low consumption. Moreover, these solutions must be scaled allowing easy adaptation in order to follow technological advances in the construction of integrated circuits. Coarse-grained reconfigurable array processors architectures allow to attend this demand, and nowadays are research focus that considers several ways to deal with its implementation, with variation of characteristics as topology, processing elements and routing capacity, among others. This work presents a placement algorithm in arrangements of processors capable to deal with variations of these characteristics, allowing early evaluation of its performance for several architectures. A test set with several DSP benchmarks was elaborated for validation. The experiments shows that the solution is fast, flexible and scalable, allowing exploration of an ample architecture spectrum before physical implementation.

ASSUNTO(S)

arquiteturas reconfiguráveis computer architecture coarse-grained processors ciencia da computacao arquitetura de computador arranjos de grão grosso reconfigurable architectures

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