Estimativa de consumo de energia em nivel de instrução para processadores modelados em ArchC / Instruction level power consumption estimation for ArchC processors
AUTOR(ES)
Josue Tzan Hsin Ma
DATA DE PUBLICAÇÃO
2007
RESUMO
The constant reduction in size and consequential increase in number of transistors inside a chip causes an exponential growth in digital circuit power consumption. Combined with the growing demand for portable electronic devices, this has led to a rising concern about energy consumption. The more power is dissipated, the more heat is generated, and the more energy is spent in the cooling process. As a result, designers have been more and more considering the impact of their decisions on this matter. Currently, ADLs¹ are being used to design new processors. These languages describe the architectural behaviour for each action or instruction. Besides decreasing the time-to-market gap, ADLs are useful in discovering architectural problems at a higher leveI. This work presents an instruction leveI power estimation tool that uses ArchC ADL as a base, and a SPARCv8 processor as a case study. By using the developed tool, a simulation of a program with estimated power consumption can be accomplished 100 times faster, in average, than the traditional tools
ASSUNTO(S)
arquitetura de computadores estimativa de potencia consumo de energia energy consumption computer architecture power estimation
