ELEMENTO DE CHAVEAMENTO PARA REDES DE INTERCONEXÃO MULTI-ESTÁGIO DE MÁQUINAS MULTIMICROPROCESSADAS / INTERCONNECTION ELEMENT FOR A PARALLEL PROCESSING SYSTEM

AUTOR(ES)
DATA DE PUBLICAÇÃO

1994

RESUMO

This work proposes a new structure of interconnection network for the MULTIPLUS, a parallel processing system under development at NCE/UFRJ. The network is fault tolerant, and works with 4 inputs and 4 outputs switches. Initially, some interconnection forms of parallel machines are discussed. Some parallel systems architecture are briefly described with emphasis on MULTIPLUS. Following, some basic concepts of interconnection networks are commented. A family tree of multistage interconnection networks, and a short history of their appearance in the literature, are presented. Some Single Path Networks, wich are related with this dissertation, are briefly described. After a deep introduction of fault tolerance, some fault- tolerant interconnection network are described. A well- structured analysis on fault tolerance gives the basis for the interconnection network proposal. The MULTIPLUS interconnection subsystem is introduced, focusing the messages´ types and structure. Various aspects regarding the proposed network - such as the topology, routing type and algorithm and, mainly, the fault- tolerance mechanism - are discussed. The design of the 4x4 switch is described in details, with emphasis on switch controllers finite state machines, but also including the priority circuit, packet counting circuit, message size compariong circuit. A detailed description of the seitch operation is given. At last, the expectede performance of a 16 inputs and 16 outpus network, where a reading message (12 packets) delay, the packet mean delay, port mean throughput, and overall mean throughput are calculated. The performance of 3 networks - one with minimum size (4x4), other with maximum size (256x256), and another with 16x16 size, each of which implemented with 2x2 and 4x4 switches - are compared. The design results are presented, including the selected EPLDs, apprximated cost of a 256x256 network implemented with the already mentioned EPLDs, and the compiling times of the switch blocks. The switch implementation in VLSI tecnology, as well the multicast communication capability, are proposed as future developments.

ASSUNTO(S)

tolerancia a falhas circuit fault tolerance circuito

ACESSO AO ARTIGO

Documentos Relacionados