Designing fault-tolerant techniques for SRAM-Based FPGAs
AUTOR(ES)
Kastensmidt, Fernanda Gusmão de Lima
DATA DE PUBLICAÇÃO
2011
ASSUNTO(S)
microeletronica fpga testes : circuitos integrados tolerancia : falhas
ACESSO AO ARTIGO
http://hdl.handle.net/10183/27593Documentos Relacionados
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