Automatic VHDL generation for solving rotation and scale-invariant template matching in FPGA. / Geração automática de módulos VHDL para localização de padrões invariante a escala e rotação em FPGA.

AUTOR(ES)

Henrique Pires Almeida Nobre

DATA DE PUBLICAÇÃO

2009

RESUMO

Template matching is a classical problem in computer vision. It consists in detecting the presence of a given template in a digital image. This task becomes considerably more complex with the invariance to rotation, scale, translation, brightness and contrast (RSTBC). A novel RSTBC-invariant robust template matching algorithm named Ciratefi was recently proposed. However, its execution in a conventional computer takes several seconds. Moreover, the implementation of its general version in hardware is difficult, because there are many adjustable parameters. This work proposes a software that automatically generates compilable Hardware Description Logic (VHDL) modules that implement the circular filter of the Ciratefi template matching algorithm in Field Programmable Gate Array (FPGA) devices. The proposed solution accelerates the time to process a frame from 7s (in a 3GHz PC) to 1.367ms (in Altera Stratix III device). This excellent performance (more than the required for a real-time system) may lead to cost-effective high-performance coprocessing computer vision systems.

ASSUNTO(S)

template matching rstbc-invariant vhdl fpga processamento de imagem computer vision fpgas vhdl template matching real time

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