A high-rate fastbus silicon strip readout system
AUTOR(ES)
Barsotti, E.
DATA DE PUBLICAÇÃO
2011
RESUMO
This paper describes a synchronous silicon S ~rePado ut system capable of zero deadtime readout at average trigger rates in excess of 1 MHz. The system is implemented in FASTBUS, uses pipelining techniques, and includes p6nt-Wpoint fiberoptic data links to transmit detector digital data. Semi-custom ASIC chips are used to amplify, discriminate, and logically combine track data before encoding. This paper describes the overall system, each major FASTBUS module, and the functional aspects of the ASIC chips.
ASSUNTO(S)
bandas paralelas saida de dados digital
ACESSO AO ARTIGO
http://hdl.handle.net/10183/27639Documentos Relacionados
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