Implementação de uma arquitetura para binarização de imagens em FPGA / Implementation of an architecture for FPGA image binarization

AUTOR(ES)
FONTE

IBICT

DATA DE PUBLICAÇÃO

13/09/2012

RESUMO

In many imaging applications it is desirable that images are converted to grayscale images to binary, ie with only two intensity levels. To accomplish this task separation between two levels is necessary to calculate a threshold value as determined from it which pixels will belong to a level generally the object of interest, and which belong to another level, or to the background image . Some applications require you to calculate this threshold value in a very short time in relation to image acquisition, especially when a very high brightness variation in the acquisition of an image. To meet this difficulty in the speed image processing applications, an alternative would be to develop an architecture dedicated to perform the calculation of the value of threshold and binarize the image acquired. This paper proposes the development of an architecture that performs these tasks by implementing reconfigurable circuits like FPGA. Making a comparison of results obtained with algorithms developed in Matlab, thus performing a validation of the proposed architecture. The developed architecture has reached the maximum frequency of 84.52 MHz, and the architecture can be operated in real-time system, using an image as a source of composite video or a regular camera.

ASSUNTO(S)

binarização binarization fpga fpga image processing otsu otsu processamento de imagens

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